Dynamic Range of Low-Voltage Cascode Current Mirrors

Low-voltage cascode current mirrors are reviewed with respect to the design limitations imposed if all transistors in the mirror are required to operate in the saturation region. It is found that both a lower limit and an upper limit exist for the cascode transistor bias voltage. Further, the use of a signal dependent cascode bias voltage is discussed and a selfbiased cascode configuration is presented. This configuration makes it possible to use a higher effective gate-source voltage for the mirror transistors, hence reducing the effect of threshold voltage mismatch on the current mirror gain. The proposed configuration has the advantage of simplicity combined with a complete elimination of the need for fixed bias voltages or bias currents in the current mirror. A disadvantage is that i t requires a higher input voltage to the current mirror.